Recessed dielectric isolation and, in particular, recessed silicon dioxide isolation are known in the large scale integrated semiconductor art for providing electrically isolated pockets on the same silicon chip, for separating base and collector contact regions of transistors constructed within isolated pockets, and for insulating conductors from the underlying silicon substrate. It is also known that recessed dielectric isolation can be produced by first selectively removing silicon from a substrate and then filling the trenches with dielectric material such as, for example, in the manner described in U.S. Pat. No. 3,966,577 issued on June 29, 1976 to A. K. Hochberg for "Dielectrically Isolated Semiconductor Devices".
In the interest of minimizing the silicon chip area occupied by the dielectrically filled trenches, sputter etching processes and reactive ion etching processes have been utilized to form the trenches in the silicon substrate. A reactive ion etching process is described in copending application Ser. No. 594,418, filed July 9, 1975, now abandoned in the name of J. M. Harvilchuck et al for "Reactive Ion Etching of Silicon" and assigned to the present assignee, to provide trenches having vertical sidewalls without significant mask undercutting and the tapered walls which are characteristic of chemical etching processes.
Reference is made to U.S. Pat. No. 4,104,086 entitled "Method for Forming Isolated Regions of Silicon Utilizing Reactive Ion Etch" granted Aug. 1, 1978 to J. A. Bondur et al and of common assignee with the subject application. The Bondur et al patent discloses a method for achieving well-filled deep narrow grooves with near vertical walls. The method consists of the formation of slightly tapered narrow grooves cut through buried highly doped Si regions, thermal oxidation of said grooves and proper filling in of the remaining grooves with a vapor deposited dielectric material. The application points out the need for forming slightly tapered walls and discusses the dependency of the quality and planarity of the dielectric filling material on the groove taper angle and groove width, respectively. The method also consists of a back etching of the filling material which covers the total wafer, with reactive ion etching to remove the material everywhere from the surface to leave only the isolation pockets.
Reference is made to U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method for Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 and of common assignee with the subject application. The Bondur et al patent discloses a method for producing deeply recessed oxidized regions in silicon. A series of deep trenches are formed in a silicon wafer by a reactive ion etching (RIE) method. In a first species, the trenches are of equal width. A block-off mask is selectively employed during part of the RIE process to produce trenches of unequal depth. The trench walls are thermally oxidized to completely fill in all of the trenches with oxide at the same time. In a second species, the trenches are of equal depth and width and of uniform spacing. In one aspect of the second species, the width of the trenches is equal to the distance between the trenches whereby the thermal oxidation completely fills in the trenches with oxide at the same time that the silicon between the trenches is fully converted to silicon oxide. In another aspect of the second species, the trenches are wider than the distance between the trenches whereby the thermal oxidation only partially fills in the trenches with oxide when the intervening silicon is fully converted to silicon oxide. In the latter aspect, the filling of the trenches is completed by the deposition of suitable material such as pyrolytically deposited silicon oxide.
Numerous techniques, methods and approaches to provide dielectric isolation in integrated circuit structures are known to the art. A representative number of which are identified and briefly discussed below.
Reference is made to U.S. Pat. No. 3,442,011 entitled "Method for Isolating Individual Devices In An Integrated Circuit Monolithic Bar" granted May 6, 1969 to F. J. Strieter. The Strieter patent discloses selective conversion of portions of a semiconductor wafer from semiconducting to insulating, leaving unconverted "pockets" of single-crystal semiconducting material isolated from each other by the insulating portions. The conversion is achieved by masking the portions of the semiconductor wafer which are to remain semiconducting, and thereafter chemically reacting the unmasked portions with oxygen, as one example, to form a new species of material (in the case of oxygen the new species would be silicon oxide) which is insulating. The pockets of unconverted semiconductor material serve as regions into which subsequent diffusions may be made or epitaxial depositions carried out in order to form diode or transistor structures, for example, of an integrated circuit, which are joined by a common substrate and yet are electrically isolated through the substrate by the insulating portions.
Reference is made to U.S. Pat. No. 3,575,740 entitled "Method of Fabricating Planar Dielectric Isolated Integrated Circuits" granted Apr. 20, 1971 to P. P. Castrucci et al. The method disclosed in the Castrucci et al patent includes etching isolation channels in a semiconductor substrate through a suitable mask. The mask pattern is designed to enhance deeper etching at certain locations in the isolation channels. A dielectric layer is formed over the exposed surfaces of the isolation channels and a semiconductor material is grown in the channels. The deeper etched locations which are now filled with dielectric isolation are used as a depth guide in the formation of a dielectric layer from the semiconductor substrate surface opposite to the one from which the etching took place. The depth guide can be used in either a deep etch or lap-back process. The last isolation step is then to continue the dielectric layer past the depth guide to the major portion of the isolation channels to produce the fully isolated islands of semiconductor material in the semiconductor substrate.
Reference is made to U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure" granted Mar. 7, 1972 to D. L. Peltzer. The Peltzer patent discloses a thin silicon epitaxial layer, formed on a silicon substrate, subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.
Reference is made to U.S. Pat. No. 3,698,966 entitled "Process Using A Masking Layer For Producing Field Effect Device Having Oxide Isolation" granted Oct. 17, 1972 to R. E. Harris. In the Harris patent oxide films and a nitride layer are selectively formed over the surface of a semiconductor wafer to define areas of the wafer in which field effect devices are to be formed. The nitride layer masks the inner oxide film as an oxide layer is formed around the masked regions to form laterally isolated semiconductor islands in which the field effect devices are to be formed. Part of the nitride layer is then used to mask the oxide film defining the gate region of the field effect device. Conductivity regions are formed in the island by diffusion as nitride layers mask the contact regions of the field effect devices. Contacts are formed on the contact regions.
Reference is made to U.S. Pat. No. 3,796,613 entitled "Method of Forming Dielectric Isolation for High Density Pedestal Semiconductor Devices" granted Mar. 12, 1974 to I. E. Magdo et al. The Magdo et al patent discloses forming dielectrically isolated pedestal semiconductor devices which are particularly adapted to form a part of an integrated circuit. The structure is useable for integrated circuits, including field effect and/or bipolar transistors wherein a significant savings in surface area and reduction in capacitance can be obtained over prior technique. The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body. An epitaxial layer of silicon is deposited on top. Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region. Polycrystalline silicon will grow on top of the dielectric material. The pedestal is formed in a single crystal epitaxial layer of another impurity type. Two other active elements of a bipolar transistor, such as the emitter and intrinsic base regions, are then formed in the same single crystal epitaxial layer while the inactive area, such as the extrinsic base, is formed in polycrystalline silicon. A reachthrough is made through the dielectric layer to the third element of the transistor, that is collector region.
Reference is made to U.S. Pat. No. 3,873,383 entitled "Integrated Circuits With Oxidation-Junction Isolation and Channel Stop" granted Mar. 25, 1975 to E. Kooi. The Kooi patent discloses a method of making a semiconductor device in a major surface of a semiconductor body having an inset pattern of insulating material and in which an additional doped zone is provided adjacent to the inset pattern. Prior to the provision of the inset pattern providing an oxidation and impurity masking layer pattern with apertures at the areas where the inset pattern is to be formed, doping the body through the apertures and thereafter oxidizing the body portions through the apertures, thereby providing oxidation-junction isolation and channel stop.
Reference is made to U.S. Pat. No. 3,886,000 entitled "Method for Controlling Dielectric Isolation of a Semiconductor Device" granted May 27, 1975 to R. L. Bratter et al. The Bratter et al patent discloses a dielectric isolation barrier formed in a silicon substrate by oxidizing openings formed in an epitaxial layer on the substrate and a layer of silicon oxynitride (SiO.sub.x N.sub.y) which is on the surface of the epitaxial layer of the substrate. During this oxidation of the openings, the layer of silicon oxynitride is thermally oxidized to form an electrically insulating layer of silicon dioxide on the surface of the epitaxial layer and homogenous with the silicon dioxide of the dielectric isolation barrier. The index of refraction of the layer of silicon oxynitride is selected in accordance with its thickness to produce a desired thickness of the layer of silicon dioxide after completion of oxidation of the openings in which the dielectric isolation barrier is formed. The index of refraction of silicon oxynitride is preferably between 1.55 and 1.70.
Reference is made to U.S. Pat. No. 3,894,893 entitled "Method for the Production of Monocrystal-Polycrystal Semiconductor Devices" granted July 15, 1975 to Y. Kabaya et al. The Kabaya et al patent discloses a method for the production of a semiconductor device, said device being composed of a plurality of polycrystalline regions and monocrystalline regions epitaxially grown on a substrate so that, between each of the two kinds of regions at least one monocrystalline to polycrystal junction is formed, whereby the conventional diffusion-type isolating process which is difficult in practice can be completely eliminated.
Reference is made to U.S. Pat. No. 3,900,350 entitled "Method of Manufacturing Semiconductor Devices in which Silicon Dioxide Regions Inset in Silicon are Formed By Masking Oxidation, wherein an Intermediate Layer of Polycrystalline Silicon is Provided Between the Substrate and the Oxidation Mask" granted Aug. 19, 1975 to J. A. Appels et al.
Reference is made to U.S. Pat. No. 3,935,328 entitled "Method for Providing Dielectric Isolation in an Epitaxial Layer of a Compound Semiconductor Using Plasma Oxidation", granted Jan. 27, 1976 to T. Sugano et al.
Reference is made to U.S. Pat. No. 3,998,673 entitled "Method for Forming Electrically-Isolated Regions in Integrated Circuits Utilizing Selective Epitaxial Growth" granted Dec. 21, 1976 to P. Chow. The Chow patent discloses a process for forming electrically-isolated regions in integrated circuits in the form of dielectric moats surrounding the regions and P-N junctions underlying the regions. Moats or notches are etched into the substrate prior to the formation of the buried isolation layer or further device information. A dielectric material such as silicon dioxide is deposited in the notches or moats and polycrystalline silicon is thereafter grown on the surface of the wafer to fill the notches or moats. The excess polysilicon formed on the surface of the wafer is then removed by mechanical lapping or polishing. Since there has been no doping or epitaxial growth, the wafer may be lapped directly to the substrate to remove all the polysilicon and oxide from the surface while leaving the notches or moats lined with dielectric material and filled with polysilicon.
Reference is made to U.S. Pat. No. 4,001,465 entitled "Process for Producing Semiconductor Devices" granted Jan. 4, 1977 to J. Graul et al. The Graul et al patent discloses a ring or lattice-shaped groove or trench etched into a surface of a Si monocrystal layer. At least one boundary of the so-etched groove or trench is coated with a strip-shaped layer of an oxidation-blocking material, such as Si.sub.3 N.sub.4 and the area of the substrate adjacent to the Si.sub.3 N.sub.4 layer and/or the substrate area enclosed by such layer is provided with a relatively thick SiO.sub.2 layer which extends deeper into the Si surface than does the SiN.sub.4 layer, while the Si surface within the groove or trench remains uncoated. The so-obtained arrangement is then thermally oxidized under conditions sufficient to at least partially fill the groove or trench with SiO.sub.2. Thereafter, the oxidation-blocking layer and at least a part of the SiO.sub.2 layer which is outside the ring or lattice-shaped trench is removed by a suitable etchant from the monocrystalline surface and the thus uncovered Si surface is further processed to produce small pn-junctions.